Scherpste prijs
Kenmerken
Auteur
Pierre Bricaud
Conditie
Gelezen
Productnummer (ISBN)
9780792381754
Jaar (oorspr.)
1998
Beschrijving
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Titel: Reuse Methodology Manual for System-on-a-Chip Designs
Auteur: Pierre Bricaud
ISBN: 9780792381754
Conditie: Beetje gebruikt
Silicon technology now allows us to build chips consisting of many millions of transistors. This technology promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see modern design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant while design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. This text outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process.
BoekenBalie maakt van tweedehands jouw eerste keuze. Met een Trustscore van 4,8 (excellent) en 30 dagen retour garantie maken we dat iedere dag waar.
Bestel direct op onze website!
Titel: Reuse Methodology Manual for System-on-a-Chip Designs
Auteur: Pierre Bricaud
ISBN: 9780792381754
Conditie: Beetje gebruikt
Silicon technology now allows us to build chips consisting of many millions of transistors. This technology promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see modern design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant while design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. This text outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process.
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Sinds 18 feb. '26
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